There are a number of signal processing applications which require that low voltage CMOS devices (for logic and sometimes analog functions) and high voltage MOS devices (typically used for switching or level shift circuits) be integrated in the same semiconductor architecture. Because of the diversity of both the types and parametric variations of the device structures, the processes used to form such combined technology architectures are often complex, sometimes requiring upwards of fifteen masking steps to pattern and layout the topography of the wafer. Moreover, as there is both an increase in cost and a decrease in yield as the number of mask steps increases, it is desirable to reduce the number of steps necessary to incorporate all of the various types of devices that make up such a multifunctional signal processing architecture.
One type of semiconductor structure that can be used to realize a high voltage MOS device in a low voltage CMOS architecture involves the addition of a lateral drift, drain-extension region to increase the reverse breakdown of the MOS structure, as described in my U.S. Pat. No. 4,823,173 entitled "High Voltage Lateral MOS Structure with Depleted Top Gate Region," issued Apr. 18, 1989, assigned to the assignee of the present application and the disclosure of which is herein incorporated. Such a lateral high voltage MOS device is diagrammatically illustrated in FIG. 1 as comprising a lateral drift, drain-extension region 11, which is contiguous with a drain region 13 and extends along the surface 14 of the body 10 of the MOS device toward a source region 12. The lateral drift region is formed beneath a thick oxide layer 15 (which may be formed by local oxidation) or under a thin (typically gate) oxide layer 17. The parameters of the drift region (e.g. doping profile in ions per square centimeter) are predefined such that, in the presence of a reverse bias applied between the drain region 13 and the body 10 (in which the channel is formed from the drift region 13 to the source region 12 beneath a gate electrode 18), the drift region becomes totally depleted of charge carriers prior to the occurrence of breakdown field in the depletion layer that extends from a reverse-biased drain-to-body PN junction 21, particularly at the sharp curvature portion 23 of the junction beneath gate electrode 18, where the total electrical field strength is increased by the presence of the bias applied to the gate. Typically, the doping per unit area of the drift region 11 is limited to a value on the order of 1 to 2.times.10.sup.12 ions/cm.sup.2 in order to satisfy this fully depleted requirement.
Thus, by adding such a lateral drift region to what is otherwise a low voltage MOS structure, the device is effectively transformed form a low voltage MOS device into a high (reverse breakdown) voltage device. Unfortunately, conventional wafer processing to provide such a lateral drift region involves both a special mask and a special doping step (e.g. ion implantation) used exclusively for the formation of the drift region, which increases the cost and complexity of the manufacturing process.